1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to synchronous semiconductor memory devices operating in synchronization with an external clock signal.
More specifically, the present invention relates to improving the reliability of a memory system configured of a synchronous semiconductor memory device provided with a synchronizing internal clock generating circuit.
2. Description of the Background Art
With the improvement of microprocessors (MPUs) in operating speed in recent years, synchronous dynamic random access memory (SDRAM) and the like operating in synchronization with a clock signal have been used to achieve rapid access to dynamic random access memory (DRAM) and the like.
FIG. 30 is a timing chart for representing an operation of such an SDRAM in inputting data.
More specifically, in response to an external clock signal ext.CLK a delay locked loop (DLL) circuit mounted in the SDRAM generates a clock signal int.CLK of a data latch portion for externally receiving data.
In generating clock signal int.CLK, a clock signal input to the DLL circuit in the SDRAM delays by an internal delay .tau.1, as compared to external clock signal ext.CLK.
There is also a delay time corresponding to a wiring delay (a time .tau.2) cause before a signal output from the DLL circuit arrives at the data latch portion in a data input portion.
Thus the DLL circuit generates an internal clock signal which previously advances by time .tau.2 in phase with respect to a rising edge of external clock signal ext.CLK. In other words, the DLL circuit outputs a clock signal advancing by a time .tau.3(=.tau.1+.tau.2) in phase as internal clock signal int.CLK.
Consequently, in a data input/output portion at the data latch portion, external and internal clock signals ext.CLK and int.CLK are signals matched in phase.
Thus, operation of the DLL circuit is calibrated so that a rising edge of external clock signal ext.CLK or a rising edge of internal clock signal int.CLK controlling the SDRAM's data receiving operation is positioned exactly at the center of an eye pattern of a data signal supplied to the SDRAM.
When a rising edge of internal clock signal ext.CLK is positioned at the center of the eye of data, operating margin will be maximized.
However, such improvement in operating margin can only be achieved when internal clock signal int.CLK is always generated reliably with respect to external clock signal ext.CLK.
Typically, however, system noise and the like often prevent the operation of generating internal clock signal int.CLK.
When system noise and the like prevent the phasing operation of the synchronizing internal clock generating circuit and locked phases of external and internal clock signals ext.CLK and int.CLK are unlocked, a data receiving margin can be degraded and a data-input error can be caused.